View HD404318S_1443667.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hd404318 series rev. 6.0 sept. 1998 description the hd404318 series is 4-bit hmcs400-series microcomputer with large-capacity memory designed to increase program productivity. each microcomputer has an a/d converter and input capture timer built in. they also come with high-voltage i/o pins that can directly drive a fluorescent display. the hd404318 series includes four chips: the hd404318 with 8-kword rom; the hd404316 with 6- kword rom; the hd404314 with 4-kword rom; the hd4074318 with 8-kword prom. the hd4074318 is a prom version ztat ? microcomputer. programs can be written to the prom by a prom writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (the prom program specifications are the same as for the 27256.) ztat ? : zero turn around time ztat is a trademark of hitachi ltd. features 34 i/o pins ? one input-only pin ? 33 input/output pins: 21 pins are high-voltage pins (40 v, max.) on-chip a/d converter (8-bit 8-channel) three timers ? one event counter input ? one timer output ? one input capture timer 8-bit clock-synchronous serial interface (1 channel) alarm output built-in oscillators ? ceramic or crystal oscillator ? external clock drive is also possible
hd404318 series 2 seven interrupt sources ? two by external sources ? three by timers ? one each by the a/d converter and serial interface two low-power dissipation modes ? standby mode ? stop mode instruction cycle time 1 m s (f osc = 4 mhz) ordering information type model name rom (words) ram (digit) package mask rom hd404314s 4,096 384 dp-42s hd404314h fp-44a hd404316s 6,144 dp-42s hd404316h fp-44a HD404318S 8,192 dp-42s hd404318h fp-44a ztat ? hd4074318s 8,192 dp-42s hd4074318h fp-44a recommended prom programmers and socket adapters prom programmer socket adapter manufacture model name package manufacturer model name data i/o corp. 121b dp-42s hitachi hs4318ess01h fp-44a hs4318esh01h aval corp. pkw-1000 dp-42s hitachi hs4318ess01h fp-44a hs4318esh01h
hd404318 series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 fp-44a test reset osc 1 osc 2 gnd av ss r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 r3 3 /an 3 r4 0 /an 4 r1 2 r8 3 r8 2 r8 1 r8 0 d 8 d 7 d 6 d 5 r1 1 r1 0 nc r0 3 r0 2 r0 1 r0 0 ra 1 /v disp r2 3 r2 2 r2 1 r2 0 r1 3 / sck /si /so /toc r4 1 /an 5 av cc v cc d 0 / int 0 d 1 / int 1 d 2 /evnb d 3 /buzz d 4 / stopc nc r4 2 /an 6 r4 3 /an 7 r0 0 / sck r0 1 /si r0 2 /so r0 3 /toc test reset osc 1 osc 2 av ss r8 3 r8 2 r8 1 r8 0 d 8 d 7 d 6 d 5 d 4 / stopc d 3 /buzz d 2 /evnb d 1 / int 1 d 0 / int 0 ra 1 /v disp r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 dp-42s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 29 28 27 26 25 24 23 22 42 41 40 39 38 37 36 35 34 33 32 31 30 v cc av cc r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 r3 3 /an 3 r4 0 /an 4 r4 1 /an 5 r4 2 /an 6 r4 3 /an 7 gnd
hd404318 series 4 pindescription pin number item symbol dp-42s fp-44a i/o function power supply v cc 21 16 applies power voltage gnd 10 5 connected to ground v disp (shared with ra 1 ) 1 39 used as a high-voltage output power supply pin when selected by the mask option test test 6 1 i cannot be used in user applications. connect this pin to gnd. reset reset 7 2 i resets the mcu oscillator osc 1 8 3 i input/output pin for the internal oscillator. connect these pins to the ceramic or crystal oscillator, or osc 1 to an external oscillator circuit. osc 2 94o port d 0 ? 8 22?0 17?1, 23?6 i/o input/output pins addressed individually by bits; d 0 ? 8 are all high-voltage i/o pins. each pin can be individually configured as selected by the mask option. ra 1 1 39 i one-bit high-voltage input port pin r0 0 ?0 3 , r3 0 ?4 3 2?, 12?9 40?3, 7?4 i/o four-bit input/output pins consisting of standard voltage pins r1 0 ?2 3 , r8 0 ?8 3 31?2 27?8 i/o four-bit input/output pins consisting of high voltage pins interrupt int 0 , int 1 22, 23 17, 18 i input pins for external interrupts stop clear stopc 26 21 i input pin for transition from stop mode to active mode serial interface sck 2 40 i/o serial interface clock input/output pin si 3 41 i serial interface receive data input pin so 4 42 o serial interface transmit data output pin timer toc 5 43 o timer output pin evnb 24 19 i event count input pin alarm buzz 25 20 o square waveform output pin a/d converter av cc 20 15 power supply for the a/d converter. connect this pin as close as possible to the v cc pin and at the same voltage as v cc . if the power supply voltage to be used for the a/d converter is not equal to v cc , connect a 0.1- m f bypass capacitor between the av cc and av ss pins. (however, this is not necessary when the av cc pin is directly connected to the v cc pin.) av ss 11 6 ground for the a/d converter. connect this pin as close as possible to gnd at the same voltage as gnd. an 0 ?n 7 12?9 7?4 i analog input pins for the a/d converter
hd404318 series 5 pin description in prom mode the hd4074318 is a prom version of a ztat ? microcomputer. in prom mode, the mcu stops operating, thus allowing the user to program the on-chip prom. pin number mcu mode prom mode dp-42s fp-44a pin i/o pin i/o 139ra 1 /v disp i 240r0 0 / sck i/o v cc 341r0 1 /si i/o v cc 442r0 2 /so i/o 543r0 3 /toc i/o 6 1 test i v pp 72 reset i reset i 8 3 osc 1 iv cc 9 4 osc 2 o 10 5 gnd gnd 11 6 av ss gnd 12 7 r3 0 /an 0 i/o o 0 i/o 13 8 r3 1 /an 1 i/o o 1 i/o 14 9 r3 2 /an 2 i/o o 2 i/o 15 10 r3 3 /an 3 i/o o 3 i/o 16 11 r4 0 /an 4 i/o o 4 i/o 17 12 r4 1 /an 5 i/o o 5 i/o 18 13 r4 2 /an 6 i/o o 6 i/o 19 14 r4 3 /an 7 i/o o 7 i/o 20 15 av cc v cc 21 16 v cc v cc 22 17 d 0 / int 0 i/o m 0 i 23 18 d 1 / int 1 i/o m 1 i 24 19 d 2 /evnb i/o a 1 i 25 20 d 3 /buzz i/o a 2 i 26 21 d 4 / stopc i/o 27 23 d 5 i/o a 3 i 28 24 d 6 i/o a 4 i 29 25 d 7 i/o a 9 i 30 26 d 8 i/o v cc
hd404318 series 6 pin number mcu mode prom mode dp-42s fp-44a pin i/o pin i/o 31 27 r8 0 i/o ce i 32 28 r8 1 i/o oe i 33 29 r8 2 i/o a 13 i 34 30 r8 3 i/o a 14 i 35 31 r1 0 i/o a 5 i 36 32 r1 1 i/o a 6 i 37 33 r1 2 i/o a 7 i 38 34 r1 3 i/o a 8 i 39 35 r2 0 i/o a 0 i 40 36 r2 1 i/o a 10 i 41 37 r2 2 i/o a 11 i 42 38 r2 3 i/o a 12 i i/o: input/output pin; i: input pin; o: output pin
hd404318 series 7 block diagram d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 r0 0 r0 1 r0 2 r0 3 d port r0 port r1 0 r1 1 r1 2 r1 3 r1 port r2 0 r2 1 r2 2 r2 3 r2 port r3 0 r3 1 r3 2 r3 3 r3 port r4 0 r4 1 r4 2 r4 3 r4 port r8 0 r8 1 r8 2 r8 3 r8 port ra 1 rom (4,096 10 bits) (6,144 10 bits) (8,192 10 bits) pc (14 bits) instruction decoder sp (10 bits) b (4 bits) a (4 bits) st (1 bit) ca (1 bit) alu spy (4 bits) y (4 bits) spx (4 bits) x (4 bits) w (2 bits) ram (384 4 bits) system control interrupt control timer a timer b timer c serial interface a/d converter buzzer internal data bus internal data bus internal address bus buzz av cc an 7 av ss an 0 si so sck toc evnb int 0 int 1 data bus high voltage pin directional signal line gnd v cc osc 2 osc 1 stopc test reset ra port
hd404318 series 8 memory map rom memory map vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000?0fff (hd404314), $0000?17ff (hd404316), $0000?1fff (hd404318, hd4074318)): the entire rom area can be used for program coding. $000f $0fff $1000 $0010 $003f $0040 vector address (16 words) zero-page subroutine (64 words) pattern (4,096 words) hd404314 program (4,096 words) hd404316 program (6,144 words) $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f 0 1 jmpl instruction (jump to reset , stopc routine) jmpl instruction (jump to int routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b routine) jmpl instruction (jump to timer c routine) jmpl instruction (jump to a/d converter routine) jmpl instruction (jump to int routine) jmpl instruction (jump to serial routine) hd404318, hd4074318 program (8,192 words) $17ff $1800 $1fff note: since the rom address areas between $0000-$0fff overlap, the user can determine how these areas are to be used. figure 1 rom memory map
hd404318 series 9 ram memorymap a/d channel register (acr) $000 $000 $040 $050 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $020 $023 $033 $034 $00a $00b $00e $00f w w r/w w w w w w w w w w r r r r w r/w r/w r/w r/w r/w $3c0 ram-mapped registers memory registers (mr) stack (64 digits) interrupt control bits area port mode register a (pmra) serial mode register (smr) serial data register lower (srl) serial data register upper (sru) timer mode register a (tma) timer mode register b1 (tmb1) timer b (trbl/twbl) (trbu/twbu) miscellaneous register (mis) timer mode register c (tmc) timer c (trcl/twcl) (trcu/twcu) register flag area port r0 dcr (dcr0) port r3 dcr (dcr3) not used 1. two registers are mapped on the same area ($00a, $00b, $00e, $00f). 2. undefined. timer read register b lower (trbl) timer read register b upper (trbu) timer read register c lower (trcl) timer read register c upper (trcu) timer write register b lower (twbl) timer write register b upper (twbu) timer write register c lower (twcl) timer write register c upper (twcu) r: read only w: write only r/w: read/write $180 notes: $016 r a/d data register lower (adrl) $017 $024 $025 $026 $018 $019 $01a $3ff a/d data register upper (adru) a/d mode register 1 (amr1) a/d mode register 2 (amr2) r w w w port mode register b (pmrb) port mode register c (pmrc) timer mode register b2 (tmb2) not used port r4 dcr (dcr4) w w w w $030 data (304 digits) not used not used not used not used -000 0000 0000 undefined undefined -000 0000 * 2 /0000 00-- 0000 0000 0000 0000 1000 0000 --00 0000 00-0 -000 0000 undefined * 2 /0000 undefined * 1 initial values after reset $03f figure 2 ram memory map and initial values
hd404318 series 10 table 1 initial values of flags after mcu reset item initial value interrupt flags/mask interrupt enable flag (ie) 0 interrupt request flag (if) 0 interrupt mask (im) 1 bit registers watchdog timer on flag (wdon) 0 a/d start flag (adsf) 0 input capture status flag (icsf) 0 input capture error flag (icef) 0 i ad off flag (iaof) 0 ram enable flag (rame) 0 bit 3 bit 2 bit 1 bit 0 imta (im of timer a) ifta (if of timer a) im1 (im of int 1 ) if1 (if of int 1 ) imtc (im of timer c) iftc (if of timer c) imtb (im of timer b) iftb (if of timer b) ims (im of serial) ifs (if of serial) imad (im of a/d) ifad (if of a/d) $0000 $0001 $0002 $0003 interrupt control bits area im0 (im of int 0 ) if0 (if of int 0 ) rsp (reset sp bit) ie (interrupt enable flag) icsf (input capture status flag) $020 $021 $022 $023 register flag area adsf (a/d start flag) wdon (watchdog on flag) not used icef (input capture error flag) rame (ram enable flag) if: interrupt request flag im: interrupt mask ie: interrupt enable flag sp: stack pointer bit 3 bit 2 bit 1 bit 0 ram address iaof (i ad off flag) not used not used figure 3 interrupt control bits and register flag areas configuration
hd404318 series 11 ie im iaof if icsf icef rame rsp wdon adsf not used sem/semd allowed not executed allowed allowed not executed not executed allowed allowed rem/remd allowed allowed not executed inhibited not executed tm/tmd allowed inhibited inhibited allowed inhibited note: wdon is reset by mcu reset or by stopc enable for stop mode cancellation. the rem or remd instruction must not be executed for adsf during a/d conversion. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 4 usage limitations of ram bit manipulation instructions memory registers $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f $3c0 $3ff mr(0) mr(1) mr(2) mr(3) mr(4) mr(5) mr(6) mr(7) mr(8) mr(9) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 mr(10) mr(11) mr(12) mr(13) mr(14) mr(15) pc pc pc pc pc pc pc pc pc pc pc pc st pc ca pc 10 3 13 9 6 2 12 8 5 1 11 7 4 0 bit 3 bit 2 bit 1 bit 0 pc ?c : st: status flag ca: carry flag program counter 13 stack area 0 $3fc $3fd $3fe $3ff figure 5 configuration of memory registers and stack area, and stack position
hd404318 series 12 registers and flags 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 6 registers and flags
hd404318 series 13 addressing modes ram addressing modes register indirect addressing mode: the contents of the w, x, and y registers (10 bits total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode (lamr, xmra): the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. 30 30 0 0 0 9 9 1 w x y opcode register indirect addressing 2nd instruction word ram address direct addressing instruction 9 0 0 9 ram address 1st instruction word 3 7 30 memory register addressing 0 9 ram address 000100 opcode instruction figure 7 ram addressing modes
hd404318 series 14 rom addressing modes direct addressing mode: a program can branch to any address in rom memory space by executing the jmpl, brl, or call instruction. current page addressing mode: a program can branch to any address in the current page (256 words per page) by executing the br instruction. zero-page addressing mode: a program can branch to any subroutine located in the zero-page subroutine area ($0000?003f) by executing the cal instruction. table data addressing mode: a program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the b register by executing the tbr instruction. 0 0 direct addressing 2nd instruction word program counter current page addressing 97 0 9 program counter 1st instruction word 50 zero-page addressing 00 operand 0 9 table data addressing 7 13 0 9 operand opcode 3 0 13 operand ****** opcode program counter 0 13 3 operand opcode ba 0 9 opcode 00000000 program counter 0 13 3 figure 8 rom addressing modes
hd404318 series 15 table 2 instruction set classification instruction type function number of instructions immediate transferring constants to the accumulator, b register, and ram. 4 register-to-register transferring contents of the b, y, spx, spy, or memory registers to the accumulator 8 ram addressing available when accessing ram in register indirect addressing mode 13 ram register transferring data between the accumulator and memory. 10 arithmetic performing arithmetic operations with the contents of the accumulator, b register, or memory. 25 compare comparing contents of the accumulator or memory with a constant 12 ram bit manipulation bit set, bit reset, and bit test. 6 rom addressing branching and jump instructions based on the status condition. 8 input/output controlling the input/output of the r and d ports; rom data reference with the p instruction 11 control controlling the serial communication interface and low-power dissipation modes. 4 total: 101 instructions
hd404318 series 16 interrupts ie if0 im0 if1 im1 ifta imta iftb imtb iftc imtc ifad imad $000,0 $000,2 $000,3 $001,0 $001,1 $001,2 $001,3 $002,0 $002,1 $002,2 $002,3 $003,0 $003,1 interrupt request priority controller ifs ims $003,2 $003,3 int 0 interrupt int 1 interrupt timer a interrupt timer b interrupt timer c interrupt a/d interrupt serial interrupt priority order vector address 1 2 3 4 5 6 7 $0000 $0002 $0004 $0006 $0008 $000a $000c $000e ( reset , stopc ) figure 9 interrupt control circuit
hd404318 series 17 instruction cycles 123456 instruction execution * ie reset interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine vector address generation note: * the stack is accessed and the ie reset after the instruction is executed, even if it is a two-cycle instruction. stacking figure 10 interrupt processing sequence
hd404318 series 18 operating modes the mcu has three operating modes as shown in table 3. transitions between operating modes are shown in figure 11. table 3 operations in each operating mode function active mode standby mode stop mode system oscillator op op stopped cpu op retained reset ram op retained retained timer a op op reset timers b, c op op reset serial interface op op reset a/d op op reset i/o op retained reset note: op implies in operation
hd404318 series 19 reset by reset input or by watchdog timer standby mode stop mode sby instruction interrupt active mode reset 1 reset 2 rame = 0 rame = 1 stop instruction stopc oscillate stop f cyc f osc : cpu : per : oscillate f cyc f cyc f osc : cpu : per : stop stop stop f osc : cpu : per : main oscillation frequency f osc /4 system clock clock for other peripheral functions f osc : f cyc : cpu : per : figure 11 mcu status transitions in stop mode, the system oscillator is stopped. to ensure a proper oscillation stabilization period of at least t rc when clearing stop mode, execute the cancellation according to the timing chart in figure12. stop mode oscillator internal clock stop instruction execution t res 3 t rc (stabilization period) t res reset or stopc figure 12 timing of stop mode cancellation
hd404318 series 20 mcu operation sequence: the mcu operates in the sequence shown in figure 13 and figure 14. the low-power mode operation sequence is shown in figure 14. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset mcu rame = 0 ie ? 0 stack ? (pc), (ca), (st) no yes if = 1? reset = 0? sby/stop instruction im = 0 ie = 1 rame = 1 instruction execution reset input pc ? vector address no no no yes yes mcu operation cycle pc ? (pc)+1 low-power mode operation cycle (figure 15) figure 13 mcu operating sequence (power on)
hd404318 series 21 low-power mode operation cycle if = 1 and im = 0? hardware nop execution ? pc next iocation mcu operation cycle standby mode if = 1 and im = 0? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes stopc = 0? rame = 1 reset mcu no yes figure 14 mcu operating sequence (low-power mode operation)
hd404318 series 22 oscillator circuit figure 15 shows a block diagram of the clock generation circuit. osc 2 osc 1 system oscillator 1/4 division circuit timing generator circuit cpu with rom, ram, registers, flags, and i/o peripheral function interrupt f cyc t cyc f osc cpu per figure 15 clock generation circuit osc 2 gnd osc 1 test reset av ss figure 16 typical layout of crystal and ceramic oscillator
hd404318 series 23 table 4 oscillator circuit examples circuit configuration circuit constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic gnd ceramic oscillator: csa4.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% crystal oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f crystal gnd l s c r s c o osc 1 osc 2 r f = 1 m w 20% c 1 = c 2 = 10 to 22 pf 20% crystal: equivalent to circuit shown below c 0 = 7 pf max. r s = 100 w max. notes: 1. since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. wiring among osc 1 , osc 2 , and elements should be as short as possible, and must not cross other wiring (see figure 16).
hd404318 series 24 i/o ports the mcu has 33 input/output pins (d 0 ? 8 , r0?4, r8) and one input-only pin (ra 1 ). the following describes the features of the i/o ports. the 21 pins consisting of d 0 ? 8 , r1, r2, and r8 are all high-voltage i/o pins. ra 1 is a high-voltage input-only pin. these high-voltage pins can be equipped with or without pull-down resistance, as selected by the mask option. all standard output pins are cmos output pins. however, the r0 2 /so pin can be programmed for nmos open-drain output. in stop mode, input/output pins go to the high-impedance state all standard input/output pins have pull-up mos built in, which can be individually turned on or off by software table 5 control of standard i/o pins by program mis3 (bit 3 of mis) 0 1 dcr 0 1 0 1 pdr 0 101 010 1 cmos buffer pmos on on nmos on ?n pull-up mos on on note: ?indicates off. bit initial value read/write bit name 3 0 w 2 0 w 0 0 w 1 0 w dcr0, dcr3, dcr4 data control register (dcr0: $030, dcr3: $033, dcr4: $034) bits 0 to 3 0 cmos buffer control cmos buffer off (high impedance) cmos buffer on register dcr0 dcr3 dcr4 bit 3 r0 3 r3 3 r4 3 correspondence between ports and dcr bits bit 2 r0 2 r3 2 r4 2 bit 1 r0 1 r3 1 r4 1 bit 0 r0 0 r3 0 r4 0 1 dcr03, dcr33, dcr43, dcr02, dcr32, dcr42, dcr01, dcr31, dcr41, dcr00, dcr30, dcr40 figure 17 data control register (dcr)
hd404318 series 25 table 6 circuit configurations of standard i/o pins i/o pin type circuit pins input/output pins v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 pdr input control signal dcr r0 0 , r0 1 , r0 3 r3 0 ?3 3 , r4 0 ?4 3 v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcr pdr input control signal mis2 r0 2 peripheral function pins input/ output pins v cc v cc pull-up control signal output data input data hlt mis3 sck sck sck output pins v cc v cc pull-up control signal pmos control signal output data hlt mis3 so mis2 so v cc v cc pull-up control signal output data hlt mis3 toc toc notes on next page.
hd404318 series 26 i/o pin type circuit pins peripheral function pins input/ pins v cc input data hlt mis3 si pdr si input control v cc hlt mis3 pdr a/d input an 0 ?n 7 notes: 1. in stop mode, the mcu is reset and the peripheral function selection is cancelled. the hlt signal goes low, and input/output pins the enter high-impedance state. 2. the hlt signal is 1 in active and standby modes.
hd404318 series 27 table 7 circuit configurations for high-voltage input/output pins i/o pin type with pull-down resistance without pull-down resistance pins input/output pins v cc input data input control signal hlt output data v disp pull-down resistance v cc input data input control signal output data hlt d 0 ? 8 , r1 0 ?1 3 , r2 0 ?2 3 , r8 0 ?8 3 input pins input data input control signal ra 1 peripheral function pins output pins v cc hlt output data v disp pull-down resistance v cc hlt output data buzz input pins input data pull-down resistance v disp input data int 0 , int 1 , evnb, stopc notes: 1. in stop mode, the mcu is reset and the peripheral function selection is cancelled. the hlt signal goes low, and input/output pins the enter high-impedance state. 2. the hlt signal is 1 in active and standby modes. 3. the circuits of hd4074318 are without pull-down resistance.
hd404318 series 28 bit initial value read/write bit name 3 0 w pmra3 2 0 w pmra2 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r0 2 /so mode selection r0 2 so port mode register a (pmra: $004) pmra1 0 1 r0 1 /si mode selection r0 1 si pmra2 0 1 r0 3 /toc mode selection r0 3 toc pmra3 0 1 d 3 /buzz mode selection d 3 buzz figure 18 port mode register a (pmra) bit initial value read/write bit name 3 0 w pmrb3 2 0 w pmrb2 0 0 w pmrb0 1 0 w pmrb1 pmrb0 0 1 d 0 / int 0 mode selection d 0 int 0 port mode register b (pmrb: $024) pmrb1 0 1 d 1 / int 1 mode selection d 1 int 1 pmrb2 0 1 d 2 /evnb mode selection d 2 evnb pmrb3 0 1 d 4 / stopc mode selection d 4 stopc * pmrb3 is reset to 0 only by reset input. when stopc is input in stop mode, pmrb3 is not reset but retains its value. note: * figure 19 port mode register b (pmrb)
hd404318 series 29 bit initial value read/write bit name note: the on/off status of each transistor and the peripheral function mode of each pin can be set independently. 3 0 w mis3 2 0 w mis2 0 not used 1 not used mis2 cmos buffer on/off selection for pin r0 2 /so miscellaneous register (mis: $00c) 0 1 cmos on cmos off mis3 0 1 pull-up mos on/off selection pull-up mos off pull-up mos on (refer to table 5) figure 20 miscellaneous register (mis)
hd404318 series 30 prescaler the mcu has a built-in prescaler labeled as prescaler s (pss), which divides the system clock and then outputs divided clock signals to the peripheral function modules, as shown in figure21. timer a timer b timer c serial system clock prescaler s clock selector figure 21 prescaler output supply
hd404318 series 31 timers the mcu has three built-in timers: a, b, and c. the functions of each timer are listed in table 7. timer a timer a is an 8-bit free-running timer that has the following features: one of eight internal clocks can be selected from prescaler s according to the setting of timer mode register a (tma: $008) an interrupt request can be generated when timer counter a (tca) overflows input clock frequency must not be modified during timer a operation table 7 timer functions functions timer a timer b timer c clock source prescaler s available available available external event available timer functions free-running available available available event counter available reload available available watchdog available input capture available timer output pwm available
hd404318 series 32 system clock selector prescaler s (pss) internal data bus timer a interrupt request flag (ifta) overflow timer counter a (tca) timer mode register a (tma) 3 per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? figure 22 timer a block diagram bit initial value read/write bit name 3 not used 2 0 w tma2 0 0 w tma0 1 0 w tma1 timer mode register a (tma: $008) 0 0 1 0 1 0 1 0 1 0 1 pss pss pss pss pss pss pss pss tma1 tma2 tma0 source prescaler input clock frequency 0 1 1 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc figure 23 timer mode register a (tma)
hd404318 series 33 timer b timer b is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features. these are described as follows. by setting timer mode register b1 (tmb1: $009), one of seven internal clocks supplied from prescaler s can be selected, or timer b can be used as an external event counter by setting timer mode register b2 (tmb2: $026), detection edge type of evnb can be selected by setting timer write register bl, bu (twbl, bu: $00a, $00b), timer counter b (tcb) can be written to during reload timer operation by setting timer read register bl, bu (trbl, bu: $00a, $00b), the contents of timer counter b can be read out timer b can be used as an input capture timer to count the clock cycles between trigger edges input as an external event an interrupt can be requested when timer counter b overflows or when a trigger input edge is received during input capture operation
hd404318 series 34 timer counter b (tcb) timer mode register b2 (tmb2) evnb selector system clock per prescaler s (pss) 2 edge detector edge detection control signal 3 timer write register b lower (twbl) timer mode register b1 (tmb1) timer write register b upper (twbu) clock free-running timer control signal timer read register b lower (trbl) interrupt request flag of timer b (iftb) timer read register bu (trbu) overflow internal data bus 2 4 8 32 128 512 2048 ? ? ? ? ? ? ? figure 24 timer b free-running and reload operation block diagram
hd404318 series 35 timer counter b (tcb) internal data bus timer mode register b2 (tmb2) evnb selector system clock per prescaler s (pss) 2 edge detector edge detection control signal 3 timer mode register b1 (tmb1) clock input capture timer control signal timer read register b lower (trbl) interrupt request flag of timer b (iftb) timer read register bu (trbu) overflow read signal input capture status flag (icsf) input capture error flag (icef) error controller 2 4 8 32 128 512 2048 ? ? ? ? ? ? ? figure 25 timer b input capture operation block diagram
hd404318 series 36 bit initial value read/write bit name 3 0 w tmb13 2 0 w tmb12 0 0 w tmb10 1 0 w tmb11 timer mode register b1 (tmb1: $009) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmb12 tmb10 tmb11 input clock period and input clock source d 2 /evnb (external event input) tmb13 0 1 free-running/reload timer selection free-running timer reload timer figure 26 timer mode register b1 (tmb1) bit initial value read/write bit name 3 not used 2 0 w tmb22 0 0 w tmb20 1 0 w tmb21 timer mode register b2 (tmb2: $026) tmb21 0 1 tmb20 0 1 0 1 evnb edge detection selection no detection falling edge detection rising edge detection rising and falling edge detection tmb22 0 1 free-running/reload and input capture selection free-running/reload input capture figure 27 timer mode register b2 (tmb2)
hd404318 series 37 timer c timer c is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are described as follows. by setting timer mode register c (tmc: $00d), one of eight internal clocks supplied from prescaler s can be selected by selecting pin toc with bit 2 (pmra2) of port mode register a (pmra: $004), timer c output (pwm output) is enabled by setting timer write register cl, cu (twcl, cu: $00e, $00f), timer counter c (tcc) can be written to by setting timer read register cl, cu (trcl, cu: $00e, $00f), the contents of timer counter c can be read out an interrupt can be requested when timer counter c overflows timer counter c can be used as a watchdog timer for detecting runaway program
hd404318 series 38 timer counter c (tcc) port mode register a (pmra) selector system clock per prescaler s (pss) 3 timer write register c lower (twcl) timer mode register c (tmc) timer write register c upper (twcu) clock free-running timer control signal timer read register c lower (trcl) interrupt request flag of timer c (iftc) timer read register cu (trcu) overflow toc timer output control signal timer output control logic watchdog timer controller watchdog on flag (wdon) system reset signal internal data bus 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? figure 28 timer c block diagram
hd404318 series 39 bit initial value read/write bit name 3 0 w tmc3 2 0 w tmc2 0 0 w tmc0 1 0 w tmc1 timer mode register c (tmc: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc2 tmc0 tmc1 input clock period tmc3 0 1 free-running/reload timer selection free-running timer reload timer 1024t cyc figure 29 timer mode register c (tmc) t (n + 1) t 256 t t (256 ?n) tmc3 = 0 (free-running timer) tmc3 = 1 (reload timer) notes: t: input clock period supplied to counter. (the clock source and system clock division ratio are determined by timer mode register c.) n: value of timer write register c. (when n = 255 ($ff), pwm output is fixed low.) figure 30 pwm output waveform
hd404318 series 40 $ff + 1 $00 timer c count value overflow time cpu operation normal operation timer c clear normal operation timer c clear program runaway normal operation reset figure 31 watchdog timer operation flowchart notes on use when using the timer output as pwm output, note the following point. from the update of the timer write register until the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 8. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle. table 8 pwm output following update of timer write register pwm output mode timer write register is updated during high pwm output timer write register is updated during low pwm output free running timer write register updated to value n interrupt request t (255 ?n) t (n + 1) timer write register updated to value n interrupt request t (n' + 1) t (255 ?n) t (n + 1) reload timer write register updated to value n interrupt request t t (255 ?n) t timer write register updated to value n interrupt request t t (255 ?n) t
hd404318 series 41 alarm output function the mcu has an alarm output function built in. by setting port mode register c (pmrc: $025), one of four alarm frequencies supplied from the pss can be selected. table 9 port mode register c pmrc bit 3 bit 2 system clock divisor 00 ? 2048 1 ? 1024 10 ? 512 1 ? 256 internal data bus ? ? ? ? 256 512 1024 2048 selector system clock per prescaler s (pss) 2 alarm output control signal buzz alarm output controller port mode register c (pmrc) port mode register a (pmra) figure 32 alarm output function block diagram
hd404318 series 42 serial interface the mcu has a one-channel serial interface built in with the following features. one of 13 different internal clocks or an external clock can be selected as the transmit clock. the internal clocks include the six prescaler outputs divided by two and by four, and the system clock. during idle states, the serial output pin can be controlled to be high or low output transmit clock errors can be detected an interrupt request can be generated after transfer has completed when an error occurs table 10 serial interface operating modes smr pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode
hd404318 series 43 internal data bus port mode register c (pmrc) sck selector system clock per prescaler s (pss) idle controller 3 serial mode register (smr) clock serial data register (sr) serial interrupt request flag (ifs) selector 1/2 1/2 si so octal counter (oc) i/o controller transfer control signal ? ? ? ? ? ? 2 8 32 128 512 2048 figure 33 serial interface block diagram
hd404318 series 44 sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) mcu reset smr write sts instruction transmit clock 8 transmit clocks or sts instruction (ifs 1) ? smr write (ifs 1) ? external clock mode sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) smr write sts instruction transmit clock sts instruction (ifs 1) ? 8 transmit clocks or internal clock mode continuous clock output state (pmra 0, 1 = 0, 0) smr write transmit clock mcu reset ? smr write (ifs 1) figure 34 serial interface state transitions lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 35 serial interface timing
hd404318 series 45 state mcu reset pmra write smr write pmrc write sck pin sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission undefined lsb msb flag reset at transfer completion external clock mode ! " state mcu reset pmra write smr write pmrc write sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states undefined lsb msb flag reset at transfer completion internal clock mode (input) instruction write srl, sru sts so pin ifs sck pin (output) instruction write srl, sru sts so pin ifs figure 36 example of serial interface operation sequence
hd404318 series 46 transmit clock erors are detected as illustrated in figure 37. transfer completion (ifs 1) interrupts inhibited ifs 0 smr write ifs = 1 transmit clock error processing normal termination ? ? yes no transmit clock error detection flowchart
transmit clock error detection procedure state sck pin (input) transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when smr is written, ifs is set. flag set because octal counter reaches 000. flag reset at transfer completion. smr write ifs 12 3 45678 figure 37 transmit clock error detection
hd404318 series 47 table 11 transmit clock selection pmrc smr bit 0 bit 2 bit 1 bit 0 system clock divisor transmit clock frequency 0000 ? 2048 4096t cyc 1 ? 512 1024t cyc 10 ? 128 256t cyc 1 ? 32 64t cyc 10 0 ? 8 16t cyc 1 ? 24t cyc 1000 ? 4096 8192t cyc 1 ? 1024 2048t cyc 10 ? 256 512t cyc 1 ? 64 128t cyc 10 0 ? 16 32t cyc 1 ? 48t cyc bit initial value read/write bit name 3 0 w smr3 2 0 w smr2 0 0 w smr0 1 0 w smr1 serial mode register (smr: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 smr2 smr0 smr1 smr3 0 1 r0 0 / sck mode selection r0 0 sck sck output input clock source prescaler external clock prescaler division ratio refer to table 11 output system clock figure 38 serial mode register (smr)
hd404318 series 48 bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 undefined w pmrc1 port mode register c (pmrc: $025) pmrc1 0 1 output level control in idle states low level high level pmrc0 0 1 serial clock division ratio prescaler output divided by 2 prescaler output divided by 4 alarm output function. refer to table 9. figure 39 port mode register c (pmrc)
hd404318 series 49 a/d converter the mcu also contains a built-in a/d converter that uses a sequential comparison method with a resistance ladder. it can perform digital conversion of eight analog inputs with 8-bit resolution. the following describes the a/d converter. a/d mode register 1 (amr1: $019) is used to select digital or analog ports a/d mode register 2 (amr2: $01a) is used to set the a/d conversion speed and to select digital or analog ports the a/d channel register (acr: $016) is used to select an analog input channel a/d conversion is started by setting the a/d start flag (adsf: $020, 2) to 1. after the conversion is completed, converted data is stored in the a/d data register, and at the same time, the a/d start flag is cleared to 0 by setting the i ad off flag (iaof: $021, 2) to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode i ad off flag (iaof) selector 3 a/d channel register (acr) a/d mode register 2 (amr2) a/d mode register 1 (amr1) a/d interrupt request flag (ifad) encoder a/d data register (adru, l) a/d start flag (adsf) d/a av cc av ss operating mode signal (1 in stop mode) internal data bus + comp a/d controller an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 control signal for conversion time 4 figure 40 a/d converter block diagram
hd404318 series 50 notes on usage use the sem or semd instruction for writing to the a/d start flag (adsf) do not write to the a/d start flag during a/d conversion data in the a/d data register during a/d conversion is undefined since the operation of the a/d converter is based on the clock from the system oscillator, the a/d converter does not operate in stop mode. in addition, to save power while in stop mode, all current flowing through the converter? resistance ladder is cut off. if the power supply for the a/d converter is to be different from v cc , connect a 0.1- m f bypass capacitor between the av cc and av ss pins. (however, this is not necessary when the av cc pin is directly connected to the v cc pin.) the port data register (pdr) is initialized to 1 by an mcu reset. at this time, if pull-up mos is selected as active by bit 3 of the miscellaneous register (mis3), the port will be pulled up to v cc . when using a shared r port/analog input pin as an input pin, clear pdr to 0. otherwise, if pull-up mos is selected by mis3 and pdr is set to 1, a pin selected by bit 1 of the a/d mode register as an analog pin will remain pulled up. bit initial value read/write bit name 3 0 w amr13 2 0 w amr12 0 0 w amr10 1 0 w amr11 amr10 0 1 an 0 a/d mode register 1 (amr1: $019) amr11 0 1 an 1 amr12 0 1 r3 2 /an 2 mode selection r3 2 an 2 amr13 0 1 r3 3 /an 3 mode selection r3 3 an 3 r3 0 /an 0 mode selection r3 0 r3 1 /an 1 mode selection r3 1 figure 41 a/d mode register 1 (amr1)
hd404318 series 51 bit initial value read/write bit name 3 not used 2 not used 0 0 w amr20 1 0 w amr21 amr20 0 1 67 t cyc a/d mode register 2 (amr2: $01a) amr21 0 1 an 4 ?n 7 conversion time 34 t cyc r4/an 4 ?n 7 pin selection r4 figure 42 a/d mode register (amr2) bit initial value read/write bit name 3 not used 2 0 w acr2 0 0 w acr0 1 0 w acr1 a/d channel register (acr: $016) 0 0 1 0 1 0 1 0 1 0 1 analog input selection an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 acr1 acr2 acr0 0 1 1 figure 43 a/d channel register (acr)
hd404318 series 52 bit initial value read/write bit name 3 not used 2 0 r/w adsf 0 not used 1 0 w wdon a/d start flag (adsf: $020, bit 2) refer to the description of timers wdon 0 1 a/d conversion completed a/d conversion started a/d start flag (adsf) figure 44 a/d start flag (adsf) bit initial value read/write bit name 3 0 r/w rame 2 0 r/w iaof 0 0 r/w icsf 1 0 r/w icef i ad off flag (iaof: $021, bit 2) refer to the description of operating modes rame refer to the description of timers icef refer to the description of timers icsf 0 1 i ad current flows i ad current is cut off i ad off flag (iaof) figure 45 i ad off flag (iaof)
hd404318 series 53 msb bit 7 lsb bit 0 result 0 1 adrl: $017 2 3 0 1 adru: $018 2 3 figure 46 a/d data registers 0 0 r adrl0 1 0 r adrl1 bit initial value read/write bit name a/d data register (lower digit) (adrl: $017) 2 0 r adrl2 3 0 r adrl3 figure 47 a/d data register lower digit (adrl) 0 0 r adru0 1 0 r adru1 bit initial value read/write bit name a/d data register (upper digit) (adru: $018) 2 0 r adru2 3 1 r adru3 figure 48 a/d data register upper digit (adru)
hd404318 series 54 notes on mounting assemble all parts including the hd404318 series on a board, noting the points described below. 1. connect layered ceramic type capacitors (about 0.1 m f) between av cc and av ss , between v cc and gnd, and between used analog pins and av ss . 2. connect unused analog pins to av ss . av an an to an av cc ss 0 1 7 av an an an to an av cc ss 0 1 2 7 av an an an to an av cc ss 0 1 2 7 1. when not using an a/d converter. v gnd cc v gnd cc v gnd cc 2. when using pins an and an but not using an to an . 01 27 3. when using all analog pins. 0.1 f 3 0.1 f 9 0.1 f figure 49 example of connections (1)
hd404318 series 55 between the v cc and gnd lines, connect capacitors designed for use in ordinary power supply circuits. an example connection is described in figure 50. no resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. the capacitors are a large capacitance c 1 and a small capacitance c 2 . v gnd cc v gnd cc c 1 c 2 figure 50 example of connections (2)
hd404318 series 56 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v 2 v cc ?45 to v cc + 0.3 v3 total permissible input current ? i o 70 ma 4 total permissible output current ? i o 150 ma 5 maximum input current i o 4 ma 6, 7 20 ma 6, 8 maximum output current ? o 4 ma 9, 10 30 ma 10, 11 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to pin test (v pp ) of hd4074318. 2. applies to all standard voltage pins. 3. applies to high-voltage pins. 4. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to gnd. 5. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 6. the maximum input current is the maximum current flowing from each i/o pin to gnd. 7. applies to ports r3 and r4. 8. applies to port r0. 9. applies to ports r0, r3, and r4. 10. the maximum output current is the maximum current flowing from v cc to each i/o pin. 11. applies to ports d 0 ? 8 , r1, r2, and r8.
hd404318 series 57 electrical characteristics dc characteristics (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition notes input high voltage v ih reset , sck , si, int 0 , int 1 , stopc , evnb 0.8v cc ? cc + 0.3 v osc 1 v cc ?0.5 v cc + 0.3 v input low voltage v il reset , sck , si ?.3 0.2v cc v int 0 , int 1 , stopc , evnb v cc ?40 0.2v cc v osc 1 ?.3 0.5 v output high voltage v oh sck , so, toc v cc ?0.5 v i oh = 0.5 ma output low voltage v ol sck , so, toc 0.4 v i ol = 0.4 ma i/o leakage current |i il | reset , sck , si, so, toc, osc 1 1 m av in = 0 v to v cc 1 int 0 , int 1 , stopc , evnb 20 m av in = v cc ?40 to v cc 1 current dissipation in active mode i cc v cc 5.0 ma v cc = 5 v, f osc = 4 mhz 2, 5 8.0 ma 2, 6 current dissipation in standby mode i sby v cc 2.0 ma v cc = 5 v, f osc = 4 mhz 3 current dissipation in stop mode i stop v cc 10 m av cc = 5 v 4, 5 20 m a 4, 6 stop mode retaining voltage v stop v cc 2v notes: 1. excludes current flowing through pull-up mos and output buffers. 2. i cc is the source current when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset , test at gnd r0, r3, r4 at v cc d 0 ? 8 , r1, r2, r8, ra 1 at v disp
hd404318 series 58 3. i sby is the source current when no i/o current is flowing while the mcu timer is operating. test conditions: mcu: i/o reset standby mode pins: reset at v cc test at gnd r0, r3, r4 at v cc d 0 ? 8 , r1, r2, r8, ra 1 at v disp 4. this is the source current when no i/o current is flowing. test conditions: pins: r0, r3, r4 at v cc d 0 ? 8 , r1, r2, r8, ra 1 at gnd 5. applies to the hd404314, hd404316 and hd404318. 6. applies to the hd4074318. i/o characteristics for standard pins (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition note input high voltage v ih r0, r3, r4 0.7v cc ? cc + 0.3 v input low voltage v il r0, r3, r4 ?.3 0.3v cc v output high voltage v oh r0, r3, r4 v cc ?0.5 v i oh = 0.5 ma output low voltage v ol r3, r4 0.4 v i ol = 1.6 ma r0 2.0 v i ol = 10 ma input leakage current |i il | r0, r3, r4 1 m av in = 0 v to v cc 1 pull-up mos ? pu r0, r3, r4 30 150 300 m av cc = 5 v, v in = 0 v 2 30 80 180 m a3 notes: 1. output buffer current is excluded. 2. applies to the hd404314, hd404316, and hd404318. 3. applies to the hd4074318.
hd404318 series 59 i/o characteristics for high-voltage pins (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition note input high voltage v ih d 0 ? 8 , r1, r2, r8, ra 1 0.7v cc ? cc + 0.3 v input low voltage v il d 0 ? 8 , r1, r2, r8, ra 1 v cc ?40 0.3v cc v output high voltage v oh d 0 ? 8 , r1, r2, r8, buzz v cc ?3.0 v i oh = 15 ma v cc ?2.0 v i oh = 10 ma v cc ?1.0 v i oh = 4 ma output low voltage v ol d 0 ? 8 , r1, r2, r8, buzz v cc ?37 v v disp = v cc ?40 v 1 v cc ?37 v 150 k w at v cc ?40 v 2 i/o leakage current |i il |d 0 ? 8 , r1, r2, r8, ra 1 , buzz 20 m av in = v cc ?40 v to v cc 3 pull-down mos current i pd d 0 ? 8 , r1, r2, r8, buzz 200 600 1000 m av disp = v cc ?35 v, v in = v cc 1 notes: 1. applies to pins with pull-down mos as selected by the mask option . 2. applies to pins without pull-down mos as selected by the mask option. 3. excludes output buffer current. a/d converter characteristics (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition note analog supply voltage av cc av cc v cc ?0.3 v cc v cc + 0.3 v 1 analog input voltage av in an 0 ?n 7 av ss ?v cc v current flowing between av cc and av ss i ad 200 m av cc = av cc = 5.0 v analog input capacitance ca in an 0 ?n 7 30 pf resolution 8 8 8 bit number of input channels 0 8 chan nel absolute accuracy 2.0 lsb conversion time 34 67 t cyc input impedance an 0 ?n 7 1m w note: 1. connect this to v cc if the a/d converter is not used.
hd404318 series 60 ac characteristics (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c) item symbol pins min typ max unit test condition note clock oscillation frequency f osc osc 1 , osc 2 0.4 4 4.5 mhz system clock divided by 4 instruction cycle time t cyc 0.89 1 10 m s oscillation stabilization time (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 1 oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 40 ms 1 external clock high width t cph osc 1 92ns 2 external clock low width t cpl osc 1 92ns 2 external clock rise time t cpr osc 1 20 ns 2 external clock fall time t cpf osc 1 20 ns 2 int 0 , int 1 , evnb high widths t ih int 0 , int 1 , evnb 2 t cyc 3 int 0 , int 1 , evnb low widths t il int 0 , int 1 , evnb 2 t cyc 3 reset low width t rstl reset 2 t cyc 4 stopc low width t stpl stopc 1 t rc 5 reset rise time t rstr reset 20 ms 4 stopc rise time t stpr stopc 20 ms 5 input capacitance c in all input pins except test 30 pf f = 1 mhz, v in = 0 v test 30 pf 6 180 pf 7 notes: 1. the oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. after v cc reaches 4.0 v at power-on. b. after reset input goes low when stop mode is cancelled. c. after stopc input goes low when stop mode is cancelled. to ensure the oscillation stabilization time at power-on or when stop mode is cancelled, reset or stopc must be input for at least a duration of t rc . when using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. refer to figure 51. 3. refer to figure 52. 4. refer to figure 53. 5. refer to figure 54. 6. applies to the hd404314, hd404316, and hd404318. 7. applies to the hd4074318.
hd404318 series 61 serial interface timing characteristics (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c, unless otherwise specified) during transmit clock output item symbol pins min typ max unit test condition note transmit clock cycle time t scyc sck 1t cyc load shown in figure 56 1 transmit clock high width t sckh sck 0.4 t scyc load shown in figure 56 1 transmit clock low width t sckl sck 0.4 t scyc load shown in figure 56 1 transmit clock rise time t sckr sck 80 ns load shown in figure 56 1 transmit clock fall time t sckf sck 80 ns load shown in figure 56 1 serial output data delay time t dso so 300 ns load shown in figure 56 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 during transmit clock input item symbol pins min typ max unit test condition note transmit clock cycle time t scyc sck 1t cyc 1 transmit clock high width t sckh sck 0.4 t scyc 1 transmit clock low width t sckl sck 0.4 t scyc 1 transmit clock rise time t sckr sck 80 ns 1 transmit clock fall time t sckf sck 80 ns 1 serial output data delay time t dso so 300 ns load shown in figure 56 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. refer to figure 55. t cpr t cpf v cc ?0.5 v 0.5 v osc 1 t cph t cpl 1/f cp figure 51 external clock timing
hd404318 series 62 0.8v cc 0.2v cc int 0 , int 1 , evnb t ih t il figure 52 interrupt timing reset t rstr t rstl 0.2v cc 0.8v cc figure 53 reset timing t stpr t stpl 0.8v cc 0.2v cc stopc figure 54 stopc timing
hd404318 series 63 0.8v cc 0.2v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.8 v v ?2.0 v cc v ?2.0 v (0.8v ) * cc 0.8 v (0.2v ) * sck so si cc cc t sckh note: * v cc -2.0v and 0.8v are the threshold voltages for transmit clock output. 0.8v cc and 0.2v cc are the threshold voltages for transmit clock input. figure 55 serial interface timing r l = 2.6 k w v cc hitachi 1s2074 or equivalent r = 12 k w test point c = 30 pf figure 56 timing load circuit
hd404318 series 64 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size for the hd404314 and hd404316 as an 8-kword version (hd404318). an 8-kword data size is required to change rom data to mask manufacturing data since the program used is for an 8-kword version. this limitation applies when using an eprom or a data base. vector address zero-page subroutine (64 words) pattern & program (4,096 words) not used vector address zero-page subroutine (64 words) pattern & program (6,144 words) not used rom 4-kword version: hd404314 address $1000?1fff rom 6-kword version: hd404316 address $1800?1fff $0000 $000f $0010 $003f $0040 $0fff $1000 $1fff $0000 $000f $0010 $003f $0040 $17ff $1800 $1fff fill this area with 1s
hd404318 series 65 hd404314/hd404316/hd404318 option list please check off the appropriate applications and enter the necessary information. 4. rom code media eprom: ceramic oscillator crystal oscillator external clock f = mhz f = mhz f = mhz 5. system oscillator for osc1 and osc2 ra1 without pull-down resistance vdisp 3. ra1/vdisp note: if even only one pin is selected with i/o option e, pin ra1/vdisp must be selected to function as vdisp. the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. dp-42s fp-44a 7. package please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). used not used 6. stop mode date of order customer department name rom code name lsi number hd404314 hd404316 hd404318 1. rom size 4-kword 6-kword 8-kword d0/ int0 d1/ int1 d2/evnb d3/buzz d4/ stopc d5 d6 d7 d8 pin name i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o option de 2. i/o options d: without pull-down resistance r1 r2 r8 ra r10 r11 r12 r13 r20 r21 r22 r23 r80 r81 r82 r83 ra1 pin name i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i i/o option de selected in option (3) e: with pull-down resistance
hd404318 series 66 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

▲Up To Search▲

Price & Availability of HD404318S

	To Download HD404318S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .